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data sheet ics843021AGI-01 revision a october 15, 2010 1 ?2010 integrated device technology, inc. femtoclock ? crystal-to-3.3v, 2.5v lvpecl clock generator ics843021i-01 general description the ics843021i-01 is a gigabit ethernet clock generator. the ics843021i-01 uses a 25mhz crystal to synthesize 125mhz. the ics843021i-01 has excellent phase jitter performance, over the 1.875mhz ? 20mhz integration range. the ics843021i-01 is packaged in a small 8-pin tssop, making it ideal for use in systems with limited board space. features ? one differential 3.3v or 2.5v lvpecl output ? crystal oscillator interface designed for 25mhz, 18pf parallel resonant crystal ? output frequency range: 125mhz, using a 25mhz crystal ? vco range: 490mhz ? 640mhz ? rms phase jitter @ 125mhz, using a 25mhz crystal (1.875mhz ? 20mhz): 0.41ps (typical) ? full 3.3v or 2.5v operating supply ? -40c to 85c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages ics843021i-01 8 lead tssop 4.40mm x 3.0mm x 0.925mm package body g package top view pin assignment 1 2 3 4 8 7 6 5 v cc xtal_out xtal_in v ee q nq v cc oe block diagram osc phase detector vco 4 (fixed) 20 (fixed) q nq xtal_in xtal_out oe pullup 25mhz
ics843021AGI-01 revision a october 15, 2010 2 ?2010 integrated device technology, inc. ics843021i-01 data sheet femtoclock ? crystal-to-3.3v, 2.5v lvpecl clock generator table 1. pin descriptions note: pullup refers to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 3a. power supply dc characteristics, v cc = 3.3v 5%, v ee = 0v, t a = -4 0c to 85c table 3b. power supply dc characteristics, v cc = 2.5v 5%, v ee = 0v, t a = -4 0c to 85c number name type description 1, 6 v cc power power supply pins. 2, 3 xtal_out xtal_in input crystal oscillator interface. xtal_i n is the input, xtal_out is the output. 4v ee power negative supply pin. 5 oe input pullup active high output enable. when logic high, the outputs are enabled and active. when logic low, the outputs are disabl ed and are in a high impedance state. lvcmos/lvttl interface levels. 7, 8 nq, q output differential output pair. lvpecl interface levels. symbol parameter test conditions minimum typical maximum units c in input capacitance 4pf r pullup input pullup resistor 51 k ? item rating supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o continuos current surge current 50ma 100ma package thermal impedance, ja 129.5 c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditio ns minimum typical maximum units v cc positive supply voltage 3.135 3.3 3.465 v i ee power supply current 64 ma symbol parameter test conditio ns minimum typical maximum units v cc positive supply voltage 2.375 2.5 2.625 v i ee power supply current 62 ma
ics843021AGI-01 revision a october 15, 2010 3 ?2010 integrated device technology, inc. ics843021i-01 data sheet femtoclock ? crystal-to-3.3v, 2.5v lvpecl clock generator table 3c. lvcmos/lvttl dc characteristics, v cc = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = 0c to 70c table 3d. lvpecl dc characteristics, v cc = 3.3v 5%, v ee = 0v, t a = -4 0c to 85c note 1: outputs termination with 50 ? to v cc ? 2v. table 3e. lvpecl dc characteristics, v cc = 2.5v 5%, v ee = 0v, t a = -4 0c to 85c note 1: outputs termination with 50 ? to v cc ? 2v. table 4. crystal characteristics symbol parameter test conditio ns minimum typical maximum units v ih input high voltage v cc = 3.3v 2 v cc + 0.3 v v cc = 2.5v 1.7 v cc + 0.3 v v il input low voltage v cc = 3.3v -0.3 0.8 v v cc = 2.5v -0.3 0.7 v i ih input high current v cc = v in = 3.465 or 2.625v 5 a i il input low current v cc = 3.465v or 2.625v, v in = 0v -150 a symbol parameter test conditions minimum typical maximum units v oh output high voltage; note 1 v cc ? 1.4 v cc ? 0.9 v v ol output low voltage; note 1 v cc ? 2.0 v cc ? 1.7 v v swing peak-to-peak output voltage swing 0.6 1.0 v symbol parameter test conditions minimum typical maximum units v oh output high voltage; note 1 v cc ? 1.4 v cc ? 0.9 v v ol output low voltage; note 1 v cc ? 2.0 v cc ? 1.5 v v swing peak-to-peak output voltage swing 0.4 1.0 v parameter test conditions minimum typical maximum units mode of oscillation fundamental frequency; note 1 25 mhz equivalent series resistance (esr) 90 ? shunt capacitance 7pf drive level 300 w
ics843021AGI-01 revision a october 15, 2010 4 ?2010 integrated device technology, inc. ics843021i-01 data sheet femtoclock ? crystal-to-3.3v, 2.5v lvpecl clock generator ac electrical characteristics table 5a. ac characteristics, v cc = 3.3v 5%, v ee = 0v, t a = -4 0c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions note 1: please refer to phase noise plot. table 5b. ac characteristics, v cc = 2.5v 5%, v ee = 0v, t a = -4 0c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions note 1: please refer to phase noise plot. symbol parameter test conditions minimum typical maximum units f out output frequency 122.5 125 160 mhz t jit(?) rms phase jitter, random; note 1 125mhz, ( integration range: 1.875mhz ? 20mhz) 0.41 ps t r / t f output rise/fall time 20% to 80% 250 600 ps odc output duty cycle 49 51 % symbol parameter test conditions minimum typical maximum units f out output frequency 122.5 125 160 mhz t jit(?) rms phase jitter, random; note 1 125mhz, ( integration range: 1.875mhz ? 20mhz) 0.42 ps t r / t f output rise/fall time 20% to 80% 250 600 ps odc output duty cycle 49 51 %
ics843021AGI-01 revision a october 15, 2010 5 ?2010 integrated device technology, inc. ics843021i-01 data sheet femtoclock ? crystal-to-3.3v, 2.5v lvpecl clock generator typical phase noise at 125mhz (3.3v or 2.5v) gigabit ethernet filter phase noise result by adding a gigabit ethernet filter to raw data raw phase noise data ? ? ? 125mhz rms phase jitter (random) 1.875mhz to 20mhz (3.3v)= 0.41ps (typical) 1.875mhz to 20mhz (2.5v)= 0.42ps (typical) noise power dbc hz offset frequency (hz)
ics843021AGI-01 revision a october 15, 2010 6 ?2010 integrated device technology, inc. ics843021i-01 data sheet femtoclock ? crystal-to-3.3v, 2.5v lvpecl clock generator parameter measureme nt information 3.3v lvpecl output load ac test circuit rms phase jitter 2.5v lvpecl output load ac test circuit output rise/fall time scope qx nqx lvpecl v ee v cc 2v -1.3v 0.165v phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power nq q t pw t period t pw t period odc = x 100% scope qx nqx lvpecl v ee v cc 2v -0.5v 0.125v 20% 80% 80% 20% t r t f v swing nq q output duty cycle/pulse width/period
ics843021AGI-01 revision a october 15, 2010 7 ?2010 integrated device technology, inc. ics843021i-01 data sheet femtoclock ? crystal-to-3.3v, 2.5v lvpecl clock generator applications information crystal input interface the ics843021i-01 has been characterized with 18pf parallel resonant crystals. the capacitor values, c1 and c2, shown in figure 1 below were determined using a 25mhz, 18pf parallel resonant crystal and were chosen to minimize the ppm error. the optimum c1 and c2 values can be slightly adjusted for different board layouts. figure 1. crystal input interface overdriving the xtal interface the xtal_in input can accept a single-ended lvcmos signal through an ac coupling capacitor. a general interface diagram is shown in figure 2a. the xtal_out pin can be left floating. the maximum amplitude of the input signal should not exceed 2v and the input edge rate can be as slow as 10ns. this configuration requires that the output impedance of t he driver (ro) plus the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and making r2 50 ? . by overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal. figure 2a. general diagram for lvcmos driver to xtal input interface figure 2b. general diagram for lvpec l driver to xtal input interface xtal_in xtal_out x1 18pf parallel crystal c1 27pf c2 27pf r2 100 r1 100 rs 43 ro ~ 7 ohm driv er_lvcmos zo = 50 ohm c1 0.1uf 3.3v 3.3v cry stal input interf ace xta l _ i n xta l _ o u t cry stal input interf ace xtal_in xtal_out r3 50 c1 0.1uf r2 50 r1 50 zo = 50 ohm lvpecl zo = 50 ohm vcc=3.3v
ics843021AGI-01 revision a october 15, 2010 8 ?2010 integrated device technology, inc. ics843021i-01 data sheet femtoclock ? crystal-to-3.3v, 2.5v lvpecl clock generator termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. the differential outputs are lo w impedance follower outputs that generate ecl/lvpecl compatible out puts. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 3a and 3b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 3a. 3.3v lvpecl output termination figure 3b. 3.3v lvpecl output termination 3.3v v cc - 2v r1 50 ? r2 50 ? rtt z o = 50 ? z o = 50 ? + _ rtt = * z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v lvpecl input r1 84 ? r2 84 ? 3.3v r3 125 ? r4 125 ? z o = 50 ? z o = 50 ? lvpecl input 3.3v 3.3v + _
ics843021AGI-01 revision a october 15, 2010 9 ?2010 integrated device technology, inc. ics843021i-01 data sheet femtoclock ? crystal-to-3.3v, 2.5v lvpecl clock generator termination for 2.5v lvpecl outputs figure 4a and figure 5b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to v cc ? 2v. for v cc = 2.5v, the v cc ? 2v is very close to ground level. the r3 in figure 4b can be eliminated and the termination is shown in figure 4c. figure 4a. 2.5v lvpecl driver termination example figure 4c. 2.5v lvpecl driver termination example figure 4b. 2.5v lvpecl driver termination example 2.5v lvpecl driver v cc = 2.5v 2.5v 2.5v 50 ? 50 ? r1 250 ? r3 250 ? r2 62.5 ? r4 62.5 ? + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 ? 50 ? r1 50 ? r2 50 ? + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 ? 50 ? r1 50 ? r2 50 ? r3 18 ? + ?
ics843021AGI-01 revision a october 15, 2010 10 ?2010 integrated device technology, inc. ics843021i-01 data sheet femtoclock ? crystal-to-3.3v, 2.5v lvpecl clock generator schematic example figure 5 shows an example of ics843021i-01 application schematic. in this example, the device is operated at v cc = 3.3v. the decoupling capacitor should be located as close as possible to the power pin. the input is driven by a 25mhz qua rtz crystal. for the lvpecl output drivers, only two termination examples are shown in this schematic. additional termination approaches are shown in the lvpecl termination application note. figure 5. ics843021i-01 schematic example r4 82.5 zo = 50 3.3v r6 82.5 + - zo = 50 r5 133 zo = 50 ohm optional termination c5 .1uf oe r3 133 r2 50 c1 27pf vcc x1 25mhz c3 10uf + - u1 843021i-01 1 2 3 4 8 7 6 5 vcc xtal_ ou t xtal_ i n vee q nq vcc oe vcc = 3.3v r1 50 zo = 50 ohm c4 .1uf r3 50 c2 27pf figure 5. ics843021i-01 schematic example
ics843021AGI-01 revision a october 15, 2010 11 ?2010 integrated device technology, inc. ics843021i-01 data sheet femtoclock ? crystal-to-3.3v, 2.5v lvpecl clock generator power considerations this section provides information on power dissipati on and junction temperature for the ics843021i-01. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics843021i-01 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. power (core) max = v cc_max * i ee_max = 3.465v * 64ma = 221.76mw power (outputs) max = 30mw/loaded output pair total power_ max (3.465v, with all outputs s witching) = 221.76mw + 30mw = 251.76mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 129.5c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.252w * 90.5c/w = 117.6c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ja for 8 lead tssop, forced convection ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 129.5c/w 1 25.5c/w 123.5c/w
ics843021AGI-01 revision a october 15, 2010 12 ?2010 integrated device technology, inc. ics843021i-01 data sheet femtoclock ? crystal-to-3.3v, 2.5v lvpecl clock generator 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 6. figure 6. lvpecl driver circuit and termination t o calculate worst case power dissipation into the load, use the following equations which assume a 50 ? load, and a termination voltage of v cc ? 2v. for logic high, v out = v oh_max = v cc_max ? 0.9v (v cc_max ? v oh_max ) = 0.9v for logic low, v out = v ol_max = v cc_max ? 1.7v (v cc_max ? v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v oh_max ) = [(2v - (v cc_max ? v oh_max ))/r l ] * (v cc_max ? v oh_max ) = [(2v - 0.9v)/50 ? ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v ol_max ) = [(2v ? (v cc_max ? v ol_max ))/r l] * (v cc_max ? v ol_max ) = [(2v ? 1.7v)/50 ? ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw v out v cc v cc - 2v q1 rl 50 ?
ics843021AGI-01 revision a october 15, 2010 13 ?2010 integrated device technology, inc. ics843021i-01 data sheet femtoclock ? crystal-to-3.3v, 2.5v lvpecl clock generator reliability information table 7. ja vs. air flow table for a 8 lead tssop transistor count the transistor count for ics843021i-01 is: 1765 package outline and package dimensions package outline - g suffix for 8 lead tssop table 8. package dimensions reference document: jede c publication 95, mo-153 ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 129.5c/w 1 25.5c/w 123.5c/w all dimensions in millimeters symbol minimum maximum n 8 a 1.20 a1 0.05 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 2.90 3.10 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 0 8 aaa 0.10
ics843021AGI-01 revision a october 15, 2010 14 ?2010 integrated device technology, inc. ics843021i-01 data sheet femtoclock ? crystal-to-3.3v, 2.5v lvpecl clock generator ordering information table 9. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 843021AGI-01 1ai01 8 lead tssop tube -40 c to 85 c 843021AGI-01t 1ai01 8 lead tssop 2500 tape & reel -40 c to 85 c 843021AGI-01lf ai01l ?lead-f ree? 8 lead tssop tube -40 c to 85 c 843021AGI-01lft ai01l ?lead-free? 8 lead tssop 2500 tape & reel -40 c to 85 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications, su ch as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not aut horize or warrant any idt product for use in life support devices or critical medical instruments.
ics843021AGI-01 revision a october 15, 2010 15 ?2010 integrated device technology, inc. ics843021i-01 data sheet femtoclock ? crystal-to-3.3v, 2.5v lvpecl clock generator revision history sheet rev table page description of change date a t9 14 ordering information table - co rrected ?temperature? column. 5/14/08 a t1 2 pin description table - corrected typo in v cc row, pins 1, 6 instead of 1, 8. 11/10/08 a t3d - t3e 3 7 lvpecl dc characteristics tables - corrected v oh /v ol parameters from ?current? to ?voltage? and units from ?ua? to ?v?. updated ?overdriving the crystal interface? section. updated header/footer. 10/15/10
ics843021i-01 data sheet femtoclock ? crystal-to-3.3v, 2.5v lvpecl clock generator disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ri sk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2010. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution

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